Analysis of information sources in references of the Wikipedia article "RISC-V" in English language version.
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{{cite web}}: CS1 maint: deprecated archival service (link)At ASTC (www.astc-design.com), we have an implementation of RV32EC as a synthesizable IP core intended for small embedded applications, such as smart sensors and IoT.
This document is a derivative of the "The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document version 1.9.1" released under following license: © 2010–2017 Andrew Waterman, Yunsup Lee, Rimas Aviˇzienis, David Patterson, Krste Asanovi ́c. Creative Commons Attribution 4.0 International License.