RISC-V (English Wikipedia)

Chen, Tony; Patterson, David (24 January 2016). RISC-V Geneology (Technical report). University of California at Berkeley. UCB/EECS-2016-6.
Samples, Alan Dain; Klein, Mike; Foley, Pete (1985). SOAR Architecture (Technical report). University of California, Berkeley. UCB/CSD-85-226.
Hill, Mark Donald; et al. (Susan J. Eggers, James Richard Larus, George S. Taylor, Glenn D. Adams, Bidyut Kumar Bose, Garth A. Gibson, Paul Mark Hansen, John Keller, Shing I. Kong, Corinna Grace Lee, Daebum Lee, J. M. Pendleton, Scott Allen Ritchie, David A. Wood, Benjamin G. Zorn, Paul N. Hilfinger, D. A. Hodges, Randy H. Katz, John K. Ousterhout, and David A. Patterson) (December 1985). SPUR: A VLSI Multiprocessor Workstation (Technical report). University of California, Berkeley. UCB/CSD-86-273.
Waterman, Andrew (13 May 2011). Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed. U.C. Berkeley: Regents of the University of California. p. 32. Retrieved 25 August 2014.
Ou, Albert; Nguyen, Quan; Lee, Yunsup; Asanović, Krste. "A Case for MVPs: Mixed-Precision Vector Processors" (PDF). UC Berkeley EECS. Regents of the University of California. Archived from the original (PDF) on 15 March 2016. Retrieved 14 March 2016.
Lee, Yunsup; Grover, Vinod; Krashinsky, Ronny; Stephenson, Mark; Keckler, Stephen W.; Asanović, Krste. "Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures" (PDF). Berkeley's EECS Site. Regents of the University of California. Archived from the original (PDF) on 15 March 2016. Retrieved 14 March 2016.

www2.eecs.berkeley.edu

Asanović, Krste; Patterson, David A. (6 August 2014). Instruction Sets Should Be Free: The Case For RISC-V (PDF). EECS Department, University of California, Berkeley. UCB/EECS-2014-146.
Asanović, Krste. "Instruction Sets Should be Free" (PDF). U.C. Berkeley Technical Reports. Regents of the University of California. Retrieved 15 November 2016.
Asanović, Krste. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA" (PDF). U.C. Berkeley Technical Reports. Regents of the University of California. Retrieved 13 May 2011.
Waterman, Andrew; Asanović, Krste (31 May 2016). "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.1" (PDF). University of California, Berkeley. EECS-2016-118. Retrieved 5 November 2021.

www-inst.eecs.berkeley.edu

Celio, Christopher. "CS 152 Laboratory Exercise 3" (PDF). UC Berkeley. Regents of the University of California. Archived from the original (PDF) on 12 February 2015. Retrieved 12 February 2015.

chisel.eecs.berkeley.edu

"Chisel: Constructing Hardware in a Scala Embedded Language". UC Berkeley. Regents of the University of California. Retrieved 12 February 2015.

canonical.com

"World's first RISC-V Laptop gets a MASSIVE upgrade and equips with Ubuntu". canonical.com. Retrieved 14 September 2024.
"World's first RISC-V Laptop gets a massive upgrade and equips with Ubuntu". canonical.com. 13 June 2024. Retrieved 19 August 2024.

cloudbear.ru

"CloudBEAR". Retrieved 16 October 2018.

cnx-software.com

"Alibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910". 20 October 2021. Retrieved 20 October 2021.
"GreenWaves GAP8 is a Low Power RISC-V IoT Processor Optimized for Artificial Intelligence Applications". CNXSoft: Embedded Systems News. 27 February 2018. Retrieved 4 March 2018.
XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 - CNX Software

codasip.com

"Codasip Studio". Codasip. Retrieved 19 February 2021.

creatorsim.github.io

CREATOR Web with RISC-V example: https://creatorsim.github.io/creator/?example_set=default_rv&example=e12

crowdsupply.com

SiFive. "Hi-Five1: Open-source Arduino-Compatible Development Kit". Crowd Supply. Retrieved 2 December 2016.

dac.com

"Design Automation Conference". dac.com. Retrieved 6 February 2021.

debian.org

wiki.debian.org

"RISC-V - Debian Wiki". wiki.debian.org. Retrieved 13 August 2024.
"RISC-V - Debian Wiki". wiki.debian.org. Retrieved 13 August 2024.

lists.debian.org

"riscv64 is now an official architecture". lists.debian.org. Retrieved 13 August 2024.

deepcomputing.io

liubing (13 April 2023). "ROMA is officially released!". DeepComputing. Retrieved 13 September 2024.
"DeepComputing Launches Early Access Program for DC-ROMA RISC-V Mainboard for Framework Laptop 13". DeepComputing. 13 November 2024. Retrieved 9 December 2024.

design-reuse.com

"Codasip Joins RISC-V Foundation and Announces Availability of RISC-V Compliant Codix Processor IP". Design And Reuse. Retrieved 9 September 2024.

docs.google.com

"Instruction Summary for a "P" ISA Proposal". Google Groups. ANDES Technologies. Retrieved 13 January 2020.
Bradbury, Alex; Wallentowitz, Stefan. "RISC-V Run Control Debug". Google Docs. RISC-V Foundation. Retrieved 20 January 2017.

doi.org

Patterson, David A.; Ditzel, David R. (October 1980). "The Case for the Reduced Instruction Set Computer". ACM SIGARCH Computer Architecture News. 8 (6): 25. doi:10.1145/641914.641917. S2CID 12034303.
Nguyen, Phuc-Vinh; Tran, Thi-Thu-Trang; Diep, Phuoc-Loc; Le, Duc-Hung (September 2018). "A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS Process". 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE. pp. 95–100. doi:10.1109/MCSoC2018.2018.00027. ISBN 978-1-5386-6689-0.
Nolting, Stephan (2022). "neorv32". GitHub. doi:10.5281/zenodo.7030070. Retrieved 9 September 2021.
Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (29 May 2024). "CREATOR: An Educational Integrated Development Environment for RISC-V Programming". IEEE Access. 12: 127702–127717. Bibcode:2024IEEEA..12l7702C. doi:10.1109/ACCESS.2024.3406935. ISSN 2169-3536.
Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Puñal, Elias; Mateos, Alejandro Calderon (23 July 2021). CREATOR: Simulador didáctico y genérico para la programación en ensamblador [CREATOR: Didactic and generic simulator for assembly programming]. XXXI Jornadas de Paralelismo (JP20/21) (in Spanish). Malaga. doi:10.5281/zenodo.5130302.
Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (October 2021). A new generic simulator for the teaching of assembly programming. 2021 XLVII Latin American Computing Conference (CLEI) (in Spanish). Cartago, Costa Rica: IEEE (published 21 December 2021). pp. 1–9. doi:10.1109/CLEI53233.2021.9640144. ISBN 978-1-6654-9503-5. S2CID 245387555. Retrieved 2 August 2022.

drive.google.com

"B Standard Extension for Bit Manipulation Instructions". RISC-V International. April 2024.

economist.com

"A new blueprint for microprocessors challenges the industry's giants". The Economist. 3 October 2019. ISSN 0013-0613. Retrieved 10 November 2019.

eejournal.com

Leibson, Steven (9 January 2023). "MIPS Rolls Out Its First RISC-V Processor Core – It's a Big 'Un". EEJournal.

eetimes.com

Dahad, Nitin (7 December 2019). "UltraSoC Tackles RISC-V Support Challenge by Donating Trace Encoder". EE Times. Aspencore. Retrieved 13 January 2020.
"At CES2022 Bouffalo Shows its Matter Turnkey Solution". www.eetimes.com. 17 January 2022. Retrieved 20 January 2022.
Yoshida, Junko (26 February 2018). "AI Comes to Sensing Devices". EE Times. Retrieved 10 July 2018.
"RV64X: A Free, Open Source GPU for RISC-V". EETimes. 27 January 2021. Retrieved 9 February 2021.
Dahad, Nitin (6 September 2021). "RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute". EE Times.
Dahad, Nitin (23 June 2020). "Siemens Acquires UltraSoC for SoC Lifecycle Product Suite". EE Times. Retrieved 12 July 2023.

eetimes.eu

"RISC-V To Move HQ to Switzerland Amid Trade War Concerns". EE Times Europe. 28 November 2019.

eevblog.com

"the-10-cent-risc-v-processor-ch32v003". EEvblog. Retrieved 10 July 2023.

electronicsweekly.com

Manners, David (23 November 2016). "Codasip and UltraSoC Combine on RISC-V". Electronics Weekly. Metropolis International Group, Ltd. Retrieved 23 November 2016.
Manners, David (8 June 2021). "Fraunhofer licensing fault-tolerant RISC core for safety-critical applications". Electronics Weekly. Retrieved 13 April 2022.

espressif.com

"3.6.2 Ultra-Low-Power Co-Processor". ESP32-S2 Family Datasheet V1.1 (PDF). Espressif Systems. 2020. Retrieved 9 June 2020.
"ESP32-C3 Family Datasheet V0.4" (PDF). Espressif Systems. 2020. Retrieved 27 December 2020.
- "Introducing ESP32-C3". Espressif (Press release). 27 November 2020.

europa.eu

commission.europa.eu

"A Europe fit for the digital age - European Commission". commission.europa.eu. 19 February 2020. Retrieved 13 August 2024.

european-processor-initiative.eu

"Accelerator Stream". European Processor Initiative (EPI). Retrieved 22 February 2020.

extremetech.com

Hruska, Joel (21 August 2014). "RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source". ExtremeTech.

fedoramagazine.org

Hanlon, Neil (19 February 2025). "RISC-V and Fedora: All Aboard!". Fedora Magazine. Retrieved 21 February 2025.

fedoraproject.org

"Architectures - Fedora Project Wiki". fedoraproject.org. Retrieved 21 February 2025.
"Architectures/RISC-V". Fedora Wiki. Red Hat. Retrieved 26 September 2016.

fossi-foundation.org

Halfacree, Gareth (14 June 2022). "CoreScore Benchmark Sees New Record with 10,000 RISC-V Cores on One FPGA". fossi-foundation.org. FOSSi Foundation. Retrieved 25 September 2023.

frame.work

"Introducing a new RISC-V Mainboard from DeepComputing". Framework. Retrieved 6 December 2024.
"RISC-V Mainboard for Framework Laptop 13 is now available". Framework. Retrieved 5 February 2025.

freebsd.org

wiki.freebsd.org

"riscv - FreeBSD Wiki". wiki.freebsd.org.

freebsdfoundation.blogspot.be

"FreeBSD Foundation: Initial FreeBSD RISC-V Architecture Port Committed". 4 February 2016.

gaisler.com

"NOEL-V Processor". Cobham Gaisler. Retrieved 14 January 2020.

gentoo.org

wiki.gentoo.org

"Project:RISC-V - Gentoo wiki". wiki.gentoo.org. Retrieved 11 February 2025.

ghostarchive.org

Xie, Joe (July 2016). NVIDIA RISC V Evaluation Story. 4th RISC-V Workshop. Youtube. Archived from the original on 13 November 2021.

gigadevice.com

"GigaDevice Unveils The GD32V Series With RISC-V Core in a Brand New 32-bit General Purpose Microcontroller". www.gigadevice.com. 23 August 2019. Archived from the original on 29 August 2019. Retrieved 29 August 2019.

github.com

Waterman, Andrew; Asanović, Krste, eds. (December 2019). "The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213" (PDF). RISC-V Foundation. Retrieved 5 November 2021.
Celio, Christopher; Love, Eric. "riscv-sodor: educational microarchitectures for risc-v isa". GitHub. Regents of the University of California. Retrieved 25 October 2019.
Waterman, Andrew; Asanović, Krste (3 December 2021). "The RISC-V Instruction Set Manual Volume II: Privileged Architecture Document Version 20211203" (PDF). RISC-V International. Retrieved 5 November 2021.
"Bit-Manipulation ISA-extensions" (PDF). RISC-V International. November 2021.
"Vector Extension". RISC-V International. November 2021.
"RISC-V Cryptography Extensions Volume I Scalar & Entropy Source Instructions" (PDF). GitHub. 18 February 2022. Retrieved 28 January 2023.
"RISC-V Profiles". Discussion. 2022.
RISC-V Platform Horizontal Subcommittee (December 2021). "RISC-V Platform Specification" (PDF). Version 0.3-draft.
"6.1.3. RVA22U64 Optional Extensions". RISC-V Profiles. RISCV. 2024.
"RVA23U64 Mandatory Base". RVA23 Profiles. RISCV. December 2024.
Newsome, Tim; Wachs, Megan (22 March 2019). "RISC-V External Debug Support Version 0.13.2 d5029366d59e8563c08b6b9435f82573b603e48e" (PDF). RISC-V International. Retrieved 7 November 2021.
Ionescu, Liviu. "The RISC-V Microcontroller Profile". GitHub. Retrieved 5 April 2018.
"riscv-aclint/riscv-aclint.adoc at main · riscv/riscv-aclint". GitHub. Retrieved 2 January 2024.
Wolf, Claire, ed. (10 January 2021). "RISC-V Bitmanip Extension Document Version 0.93" (PDF). GitHub. RISC-V Foundation. Retrieved 9 March 2021.
"Release Vector Extension 1.0, frozen for public review · riscv/Riscv-v-spec". GitHub.
McGooganus. "riscv-trace-spec". GitHub. Retrieved 13 January 2020.
"RISC-V Cores and SoC Overview". RISC-V. 25 September 2019. Retrieved 5 October 2019.
riscv/riscv-cores-list, RISC-V, 6 February 2021, retrieved 9 February 2021
"SCR1 is a high-quality open-source RISC-V MCU core in Verilog". GitHub. Syntacore. Retrieved 13 January 2020.
"PULPino GitHub project". GitHub. Retrieved 2 February 2018.
Asanović, Krste; et al. "rocket-chip". GitHub. RISC-V International. Retrieved 11 November 2016.
Celio, Christopher. "riscv-boom". GitHub. Regents of the University of California. Retrieved 29 March 2020.
XiangShan repository on Github
Wolf, Claire. "PicoRV32 - A Size-Optimized RISC-V CPU". GitHub. Retrieved 27 February 2020.
"MIPT-MIPS: Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs". GitHub.
Kindgren, Olof. "SERV - The serial RISC-V CPU". GitHub. Retrieved 25 September 2023.
Cores-SweRV on GitHub
Nolting, Stephan (2022). "neorv32". GitHub. doi:10.5281/zenodo.7030070. Retrieved 9 September 2021.
Wren, Luke (8 August 2024), Wren6991/Hazard3, retrieved 8 August 2024
RiscVEdk2 on GitHub
Almatary, Hesham. "heshamelmatary". GitHub. Retrieved 13 July 2018.
CREATOR source code on GitHub: https://github.com/creatorsim/creator
riscv/riscv-compliance, RISC-V, 12 February 2021, retrieved 19 February 2021

gizmochina.com

"World's First RISC-V Laptop Roma Officially Delivered: 8GB RAM and Pre-installed with Domestic OS". Gizmochina. 17 August 2023. Retrieved 13 September 2024.

golem.de

"Golem.de: IT-News für Profis". www.golem.de. Retrieved 19 May 2025.

googleblog.com

security.googleblog.com

Kleidermacher, Dave; Seed, Jesse; Barbello, Brandon (27 October 2021). "Pixel 6: Setting a new standard for mobile security". Google Security Blog. Archived from the original on 27 October 2021. Retrieved 12 February 2023.

greenwaves-technologies.com

"GreenWaves Technologies Announces Availability of GAP8 Software Development Kit and GAPuino Development Board" (Press release). 22 May 2018.

groups.google.com

Brussee, Rogier. "A Complete 16-bit RVC". Google Groups. RISC-V Foundation. Retrieved 18 July 2019.
Brussee, Rogier. "Proposal: Xcondensed, [a] ... Compact ... 16 bit standalone G-ISA". RISC-V ISA Mail Server. Google Groups. Retrieved 10 November 2016.
Phung, Xan. "Improved Xcondensed". Google Groups. RISC-V Foundation. Retrieved 18 July 2019.
Barros, Cesar (1 April 2018). "Proposal: RV16E". RISC-V ISA Developers (Mailing list). Retrieved 2 April 2018.
Bonzini, Paolo; Waterman, Andrew. "Proposal for Virtualization without H mode". RISC-V ISA Developers (Mailing list). Retrieved 24 February 2017.
Newsome, Tim. "RISC-V Debug Group > poll results". Google Groups, RISC-V Debug Group. RISC-V Foundation. Retrieved 20 January 2017.
Ashenden, Peter (9 November 2016). "Re: [isa-dev] RISC V ISA for embedded systems". RISC-V ISA Developers (Mailing list). Retrieved 10 November 2016. At ASTC (www.astc-design.com), we have an implementation of RV32EC as a synthesizable IP core intended for small embedded applications, such as smart sensors and IoT.
Montezelo, Manuel. "Debian GNU/Linux port for RISC-V 64". Google Groups. Retrieved 19 July 2018.
Begari, Padmarao. "U-Boot port on RISC-V 32-bit is available". Google Groups. Microsemi. Retrieved 15 February 2017.

hackster.io

"Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning". 15 November 2019.

haiku-os.org

"Booting our RISC-V images". Haiku Project. 7 November 2021. Retrieved 4 March 2023.

harvard.edu

ui.adsabs.harvard.edu

Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (29 May 2024). "CREATOR: An Educational Integrated Development Environment for RISC-V Programming". IEEE Access. 12: 127702–127717. Bibcode:2024IEEEA..12l7702C. doi:10.1109/ACCESS.2024.3406935. ISSN 2169-3536.

heise.de

"270 Millionen Euro für CPUs und Beschleuniger: EuroHPC fördert RISC-V-Technik". heise online (in German). 21 December 2022. Retrieved 13 August 2024.
"Offengelegter RISC-V-Chip aus China soll an ARM Cortex-A76 heranreichen". c't Magazin (in German). 30 June 2021. Retrieved 13 August 2024.
online, heise (13 October 2021). "Alibabas RISC-V-Prozessor XuanTie C910 lieferbar". c't Magazin (in German). Retrieved 14 September 2024.

hex-five.com

"MultiZone Secure IoT Stack, the First Secure IoT Stack for RISC-V". Hex Five Security. Hex Five Security, Inc. 22 February 2019. Retrieved 3 March 2019.

hpcwire.com

"China Is All In on a RISC-V Future". 8 January 2024. Retrieved 7 May 2024.

ieee.org

ieeexplore.ieee.org

Nguyen, Phuc-Vinh; Tran, Thi-Thu-Trang; Diep, Phuoc-Loc; Le, Duc-Hung (September 2018). "A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS Process". 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE. pp. 95–100. doi:10.1109/MCSoC2018.2018.00027. ISBN 978-1-5386-6689-0.
Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (October 2021). A new generic simulator for the teaching of assembly programming. 2021 XLVII Latin American Computing Conference (CLEI) (in Spanish). Cartago, Costa Rica: IEEE (published 21 December 2021). pp. 1–9. doi:10.1109/CLEI53233.2021.9640144. ISBN 978-1-6654-9503-5. S2CID 245387555. Retrieved 2 August 2022.

iitm.ac.in

"IIT Madras Develops and Boots up MOUSHIK Microprocessor for IoT Devices". IIT Madras. 24 September 2020. Retrieved 9 July 2021.

imaginationtech.com

"IMG RTXM-2200 CPU". Imagination. Retrieved 30 September 2023.

indiatimes.com

timesofindia.indiatimes.com

"C-DAC announces Tech Conclave 2019". The Times of India. Archived from the original on 17 May 2019. Retrieved 12 April 2019.

indiatoday.in

Tripathi, Sibu Kumar (11 February 2025). "Isro and IIT Madras develop indigenous semiconductor chip". India Today. Retrieved 11 February 2025.

jamestown.org

Cheung, Sunny (15 December 2023). "Examining China's Grand Strategy For RISC-V". China Brief. Jamestown Foundation. Retrieved 18 December 2023.
"Examining China's Grand Strategy For RISC-V". jamestown.org. Retrieved 13 August 2024.

kernel.org

docs.kernel.org

"CPU Architectures — The Linux Kernel documentation". docs.kernel.org. Retrieved 20 August 2024.

lauterbach.com

"RISC-V Debugger". www.lauterbach.com TRACE32 Debugger for RISC-V.
"TRACE32 supports SiFive's RISC-V trace". www.lauterbach.com. Archived from the original on 2 June 2022. Retrieved 6 March 2021.

linleygroup.com

"The Linley Group Announces Winners of Annual Analysts' Choice Awards" (Press release). The Linley Group. 12 January 2017. Retrieved 21 January 2018.

linuxgizmos.com

Brown, Eric (8 December 2021). "Two 64-bit RISC-V cores debut: StarFive Dubhe and CAS Nanhu". LinuxGizmos.com. Retrieved 13 August 2024.

live-risc-v.pantheonsite.io

Lee, Yunsup (5 March 2014). "Boot RISC-V Linux in your web browser!". RISC-V International. Retrieved 4 September 2020.

lowrisc.org

"lowRISC website". Retrieved 10 May 2015.

missouristate.edu

courses.missouristate.edu

"MIPS syscall functions available in MARS". courses.missouristate.edu. Retrieved 28 May 2023.

newelectronics.co.uk

"Codasip announces RISC-V processor cores providing multi-core and SIMD capabilities". www.newelectronics.co.uk. Archived from the original on 23 December 2020. Retrieved 9 February 2021.

opencores.org

"Amber ARM-compatible core". OpenCores. Retrieved 26 August 2014.
"ARM4U". OpenCores. Retrieved 26 August 2014.

opensuse.org

en.opensuse.org

"openSUSE Project Wiki". opensuse.org. Retrieved 25 February 2025.
"RISC-V Portal". openSUSE Wiki. openSUSE. Retrieved 21 June 2021.

hackweek.opensuse.org

"RISC-V boot deep dive". openSUSE Hackweek.

org.s3-website-us-west-1.amazonaws.com

riscv.org.s3-website-us-west-1.amazonaws.com

"ANGEL – RISC-V". riscv.org.s3-website-us-west-1.amazonaws.com. Archived from the original on 1 December 2020. Retrieved 4 September 2020.

prnewswire.com

SpacemiT. "RISC-V Breakthrough: SpacemiT Develops Server CPU Chip V100 for Next-Generation AI Applications". www.prnewswire.com (Press release). Retrieved 20 January 2025.

pulp-platform.org

"PULP Platform". PULP Platform. Retrieved 2 February 2018.
Traber, Andreas; et al. "PULP: Parallel Ultra Low Power". ETH Zurich, University of Bologna. Retrieved 5 August 2016.

qemu.org

wiki.qemu.org

"Documentation/Platforms/RISCV". QEMU Wiki. Retrieved 7 May 2020.

rapidio.org

"IIT Madras Open Source Processor Project". Rapid IO. IIT Madras. 26 August 2014. Archived from the original on 14 September 2014. Retrieved 13 September 2014.

raspberrypi.com

Upton, Eben (8 August 2024). "Raspberry Pi Pico 2, our new $5 microcontroller board, on sale now". Retrieved 8 August 2024.

reuters.com

"U.S.-based chip-tech group moving to Switzerland over trade curb fears". Reuters. 26 November 2019. Retrieved 26 November 2019.
Horwitz, Josh (23 March 2023). "Chinese search giant Baidu invests in RISC-V chip technology startup StarFive". Reuters.

riscv.org

"About RISC-V". RISC-V International.
"Frequently Asked Questions (FAQ) – RISC-V International". Retrieved 20 August 2024.
"Linux 5.17 Adds Support For "The First Usable, Low-Cost RISC-V Platform" | Michael Larabel, Phoronix – RISC-V International". 2022. Retrieved 20 August 2024.
"Contributors". riscv.org. Regents of the University of California. Archived from the original on 7 September 2018. Retrieved 25 August 2014.
"RISC-V History". Retrieved 28 January 2023.
"Members". RISC-V International. Retrieved 1 August 2023.
"RISC-V History - RISC-V International". RISC-V International. Retrieved 14 May 2020.
"Branding Guidelines – RISC-V International". Retrieved 23 June 2024.
"Rocket Core Generator". RISC-V. Regents of the University of California. Archived from the original on 6 October 2014. Retrieved 1 October 2014.
Waterman, Andrew; Asanović, Krste (7 May 2017). "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2" (PDF). RISC-V International. Retrieved 5 November 2021.
Waterman, Andrew; et al. "The RISC-V Compressed Instruction Set Manual Version 1.9 (draft)" (PDF). RISC-V. Retrieved 18 July 2016.
Su, Charlie (30 June 2018). "Comprehensive RISC-V Solutions for AIoT" (PDF). RISC-V Content. RISC-V Foundation. Retrieved 28 January 2023.
Schmidt, Colin; Ou, Albert; Lee, Yunsup; Asanović, Krste. "RISC-V Vector Extension Proposal" (PDF). RISC-V. Regents of the University of California. Retrieved 14 March 2016.
"RISC-V International Members". RISC-V International. Retrieved 22 January 2021.
"RISC-V workshop proceedings". 11 December 2016. Retrieved 28 January 2023.
Redmond, Calista (28 January 2023). "How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing". RISC-V International News. RISC-V International.
anisha. "World's first RISC-V Laptop gets a MASSIVE upgrade and equips with Ubuntu – RISC-V International". Retrieved 14 September 2024.
"ANGEL is a Javascript RISC-V ISA (RV64) Simulator that runs riscv-linux with BusyBox". RISCV.org. Archived from the original on 11 November 2018. Retrieved 17 January 2019.

sdxcentral.com

StringerAI™ (9 January 2025). "SpacemiT Develops Server CPU Chip V100 for Next-Gen AI Applications". SDxCentral. Retrieved 20 January 2025.

seeedstudio.com

"Sipeed Longan Nano - RISC-V GD32VF103CBT6 Development Board". www.seeedstudio.com. Retrieved 29 August 2019.

segger.com

"SEGGER Adds Support for SiFive's Coreplex IP to Its Industry Leading J-Link Debug Probe". Retrieved 19 September 2017.
"PR: SEGGER Embedded Studio supports RISC-V architecture". Retrieved 23 November 2017.
"PR: SEGGER presents RTOS, stacks, middleware for RISC-V". Retrieved 8 December 2017.

sel4.systems

docs.sel4.systems

Almatary, Hesham. "RISC-V, seL4". seL4 Documentation. Commonwealth Scientific and Industrial Research Organisation (CSIRO). Retrieved 13 July 2018.

semanticscholar.org

api.semanticscholar.org

Patterson, David A.; Ditzel, David R. (October 1980). "The Case for the Reduced Instruction Set Computer". ACM SIGARCH Computer Architecture News. 8 (6): 25. doi:10.1145/641914.641917. S2CID 12034303.
Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (October 2021). A new generic simulator for the teaching of assembly programming. 2021 XLVII Latin American Computing Conference (CLEI) (in Spanish). Cartago, Costa Rica: IEEE (published 21 December 2021). pp. 1–9. doi:10.1109/CLEI53233.2021.9640144. ISBN 978-1-6654-9503-5. S2CID 245387555. Retrieved 2 August 2022.

semiaccurate.com

Demerjian, Chuck (7 August 2013). "A long look at how ARM licenses chips: Part 1". SemiAccurate.
Demerjian, Chuck (8 August 2013). "How ARM licenses its IP for production: Part 2". SemiAccurate.

semiengineering.com

Urquhart, Roddy (29 March 2021). "What Does RISC-V Stand For? A brief history of the open ISA". Systems & Design: Opinion. Semiconductor Engineering.

servethehome.com

"Esperanto ET-SoC-1 1092 RISC-V AI Accelerator Solution at Hot Chips 33". 24 August 2021.

shakti.org.in

"SHAKTI Processor Program". Indian Institute of Technology Madras. Retrieved 3 September 2019.

sifive.com

"HiFive1". SiFive. Archived from the original on 26 February 2017. Retrieved 10 July 2018.
"FU540 SoC CPU". SiFive. Archived from the original on 5 October 2018. Retrieved 24 October 2018.
"Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores". www.sifive.com.

sourceforge.net

"Pharos". SourceForge. Retrieved 1 April 2020.

spacemit.com

developer.spacemit.com

"进迭时空开发者社区". developer.spacemit.com. Retrieved 10 December 2024.

syntacore.com

"Syntacore". Retrieved 11 December 2018.

techcrunch.com

Lardinois, Frederic (31 May 2023). "The Linux Foundation Europe launches RISE, the RISC-V Software Ecosystem project". TechCrunch. Retrieved 13 December 2024.

techspot.com

"China's Alibaba is making a 16-core, 2.5 GHz RISC-V processor". www.techspot.com. 28 July 2019. Retrieved 30 July 2019.

thehindu.com

Desikan, Shubashree (6 August 2018). "IIT-Madras powers up a desi chip". The Hindu. ISSN 0971-751X. Retrieved 25 September 2020.

theregister.com

Connatser, Matthew (13 August 2024). "Akeana debuts RISC-V CPU designs on $100M budget, longs for an Arm wrestle". The Register. Retrieved 19 August 2024.
Connatser, Matthew. "World's first RISC-V laptop with Ubuntu preloaded touts AI smarts and octa-core chip". The Register. Retrieved 19 August 2024.
"Alibaba launches server-grade RISC-V CPU design". Archived from the original on 16 March 2025. Retrieved 19 May 2025.
"Alibaba launches server-grade RISC-V CPU design". Archived from the original on 11 April 2025. Retrieved 19 May 2025.
Robinson, Dan (11 May 2022). "MIPS discloses first RISC-V chips coming in Q4 2022". The Register.
Sharwood, Simon (27 March 2023). "Chinese web giant Baidu backs RISC-V for the datacenter". The Register.
Dobberstein, Laura. "India's homebrew RISC-V CPU debuts in cheap dev board". The Register. Retrieved 6 March 2024.
Sharwood, Simon (19 August 2020). "India selects RISC-V for semiconductor self-sufficiency contest: Use these homegrown cores to build kit". The Register. Retrieved 9 July 2021.
Halfacree, Gareth (10 June 2021). "RISC-V boffins lay out a plan for bringing the architecture to high-performance computing". The Register. Retrieved 9 July 2021.
Halfacree, Gareth (6 July 2021). "Chinese chip designers hope to topple Arm's Cortex-A76 with XiangShan RISC-V design". The Register. Retrieved 13 August 2024.

tomshardware.com

Anton Shilov (20 March 2024). "Alibaba claims it will launch a server-grade RISC-V processor this year". Tom's Hardware. Retrieved 19 August 2024.
Aleksandar Kostovic (12 July 2021). "Libre-SOC Releases First Non-IBM OpenPOWER Chip in Decade". Tom's Hardware. Retrieved 20 August 2024.
Anton Shilov (14 January 2025). "China's SpacemiT develops 64-core RISC-V datacenter CPU on 12nm". Tom's Hardware. Retrieved 20 January 2025.
published, Anton Shilov (14 January 2025). "China's SpacemiT develops 64-core RISC-V datacenter CPU on 12nm". Tom's Hardware. Retrieved 8 June 2025.
Shilov, Anton (9 December 2020). "Seagate Develops Own RISC-V Cores for Storage Controllers". Tom's Hardware.
Ian Evenden (4 October 2022). "World's First Laptop with RISC-V Processor Now Available". Tom's Hardware. Retrieved 14 September 2024.
Jowi Morales (13 June 2024). "The world's first RISC-V laptop gets a big upgrade — DeepComputing doubled the core count, increased clocks to 2 GHz, and added AI capabilities". Tom's Hardware. Retrieved 14 September 2024.
Jowi Morales (13 June 2024). "The world's first RISC-V laptop gets a big upgrade — DeepComputing doubled the core count, increased clocks to 2 GHz, and added AI capabilities". Tom's Hardware. Retrieved 27 November 2024.

vegaprocessors.in

"VEGA MICROPROCESSORS". Vega Processor - CDAC. 9 July 2021. Archived from the original on 9 July 2021. Retrieved 9 July 2021.

wch-ic.com

"WinChipHead (WCH)".
"CH32V003". WCH-IC. Retrieved 10 July 2023.

web.archive.org

"Contributors". riscv.org. Regents of the University of California. Archived from the original on 7 September 2018. Retrieved 25 August 2014.
"Rocket Core Generator". RISC-V. Regents of the University of California. Archived from the original on 6 October 2014. Retrieved 1 October 2014.
Celio, Christopher. "CS 152 Laboratory Exercise 3" (PDF). UC Berkeley. Regents of the University of California. Archived from the original (PDF) on 12 February 2015. Retrieved 12 February 2015.
Ou, Albert; Nguyen, Quan; Lee, Yunsup; Asanović, Krste. "A Case for MVPs: Mixed-Precision Vector Processors" (PDF). UC Berkeley EECS. Regents of the University of California. Archived from the original (PDF) on 15 March 2016. Retrieved 14 March 2016.
Lee, Yunsup; Grover, Vinod; Krashinsky, Ronny; Stephenson, Mark; Keckler, Stephen W.; Asanović, Krste. "Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures" (PDF). Berkeley's EECS Site. Regents of the University of California. Archived from the original (PDF) on 15 March 2016. Retrieved 14 March 2016.
"Alibaba launches server-grade RISC-V CPU design". Archived from the original on 16 March 2025. Retrieved 19 May 2025.
"HiFive1". SiFive. Archived from the original on 26 February 2017. Retrieved 10 July 2018.
"FU540 SoC CPU". SiFive. Archived from the original on 5 October 2018. Retrieved 24 October 2018.
"Alibaba launches server-grade RISC-V CPU design". Archived from the original on 11 April 2025. Retrieved 19 May 2025.
"Codasip announces RISC-V processor cores providing multi-core and SIMD capabilities". www.newelectronics.co.uk. Archived from the original on 23 December 2020. Retrieved 9 February 2021.
"GigaDevice Unveils The GD32V Series With RISC-V Core in a Brand New 32-bit General Purpose Microcontroller". www.gigadevice.com. 23 August 2019. Archived from the original on 29 August 2019. Retrieved 29 August 2019.
Kleidermacher, Dave; Seed, Jesse; Barbello, Brandon (27 October 2021). "Pixel 6: Setting a new standard for mobile security". Google Security Blog. Archived from the original on 27 October 2021. Retrieved 12 February 2023.
"C-DAC announces Tech Conclave 2019". The Times of India. Archived from the original on 17 May 2019. Retrieved 12 April 2019.
"VEGA MICROPROCESSORS". Vega Processor - CDAC. 9 July 2021. Archived from the original on 9 July 2021. Retrieved 9 July 2021.
"IIT Madras Open Source Processor Project". Rapid IO. IIT Madras. 26 August 2014. Archived from the original on 14 September 2014. Retrieved 13 September 2014.
"Western Digital Releases SweRV RISC-V Core Source Code". AB Open. 28 January 2019. Archived from the original on 21 May 2019.
"ANGEL is a Javascript RISC-V ISA (RV64) Simulator that runs riscv-linux with BusyBox". RISCV.org. Archived from the original on 11 November 2018. Retrieved 17 January 2019.
"ANGEL – RISC-V". riscv.org.s3-website-us-west-1.amazonaws.com. Archived from the original on 1 December 2020. Retrieved 4 September 2020.
"TRACE32 supports SiFive's RISC-V trace". www.lauterbach.com. Archived from the original on 2 June 2022. Retrieved 6 March 2021.

wepsim.github.io

"WepSIM with RISC-V_im example". WepSIM.
"WepSIM homepage".

wikichip.org

fuse.wikichip.org

"Esperanto exits stealth mode, aims at AI with a 4,096 core 7nm RISC-V monster". wikichip.org. January 2018. Retrieved 2 January 2018.

wionews.com

"Meet India's Atmanirbhar Microprocessor chip 'Moushik', meant for IoT devices". WION. 24 September 2020. Retrieved 25 September 2020.

worldcat.org

search.worldcat.org

"A new blueprint for microprocessors challenges the industry's giants". The Economist. 3 October 2019. ISSN 0013-0613. Retrieved 10 November 2019.
Desikan, Shubashree (6 August 2018). "IIT-Madras powers up a desi chip". The Hindu. ISSN 0971-751X. Retrieved 25 September 2020.
Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (29 May 2024). "CREATOR: An Educational Integrated Development Environment for RISC-V Programming". IEEE Access. 12: 127702–127717. Bibcode:2024IEEEA..12l7702C. doi:10.1109/ACCESS.2024.3406935. ISSN 2169-3536.

youtube.com

Xie, Joe (July 2016). NVIDIA RISC V Evaluation Story. 4th RISC-V Workshop. Youtube. Archived from the original on 13 November 2021.

zenodo.org

Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Puñal, Elias; Mateos, Alejandro Calderon (23 July 2021). CREATOR: Simulador didáctico y genérico para la programación en ensamblador [CREATOR: Didactic and generic simulator for assembly programming]. XXXI Jornadas de Paralelismo (JP20/21) (in Spanish). Malaga. doi:10.5281/zenodo.5130302.