Analysis of information sources in references of the Wikipedia article "펜티엄 프로" in Korean language version.
Integer Leads, FP Lags RISC Chips
The P6 lineage from the Pentium Pro to the Pentium M [...] One of the most distinctive features of the P6 line is its issue port structure. (Intel calls these "dispatch ports," but for the sake of consistency with the rest of my work I'll be using the terms "dispatch" and "issue" differently than Intel.) Core uses a similar structure in its execution core, although there are some major differences between Core's issue port and RS combination and that of the P6.
There were a lot of pieces involved in this chip but today’s Pentium Pro consists of two chips and other needed support chips too. Curiously the lead engineer for the 432 was superstar designer Fred Pollack who became the lead architect for the Pentium Pro.
Offenbar hat der PPro einen ladbaren Microcode, für den das Board-BIOS zwei Funktionen im Interrupt 15h zum Auslesen und Laden bereithält (näheres im nächsten Update der Interrupt-Liste). Gedacht ist das für Patches, doch wer weiß, welch ungeahnte Möglichkeiten noch darinstecken. Somit hat man es beim PPro in Zukunft nicht nur mit zwei Masken-Versionen (für CPU und Cache), sondern auch noch mit der Update-Version des Microcode-BIOS zu tun (zum Beispiel beim aktuellen 200-MHz-'P6S' mit der Kennung SY013: CPU-Step A0, Cache-Step B1, BIOS: sA0C05).
The Intel Corporation today introduced its new microprocessor, the Pentium Pro. But although the chip's performance is higher than expected, and its price lower, analysts said its immediate impact was not likely to match that of its predecessor, the Pentium.
Intel’s ASCI Red supercomputer was the first teraflop/s computer, taking the No.1 spot on the 9th TOP500 list in June 1997 with a Linpack performance of 1.068 teraflop/s. [...] It was a mesh-based (38 X 32 X 2) MIMD massively parallel machine initially consisting of 7,264 compute nodes, 1,212 gigabytes of total distributed memory and 12.5 terabytes of disk storage. The original incarnation of this machine used Intel Pentium Pro processors, each clocked at 200 MHz. These were later upgraded to Pentium II OverDrive processors. The system was upgraded to a total of 9,632 Pentium II Over-Drive processors, each clocked at 333 MHz.
The Intel Corporation today introduced its new microprocessor, the Pentium Pro. But although the chip's performance is higher than expected, and its price lower, analysts said its immediate impact was not likely to match that of its predecessor, the Pentium.
Intel’s ASCI Red supercomputer was the first teraflop/s computer, taking the No.1 spot on the 9th TOP500 list in June 1997 with a Linpack performance of 1.068 teraflop/s. [...] It was a mesh-based (38 X 32 X 2) MIMD massively parallel machine initially consisting of 7,264 compute nodes, 1,212 gigabytes of total distributed memory and 12.5 terabytes of disk storage. The original incarnation of this machine used Intel Pentium Pro processors, each clocked at 200 MHz. These were later upgraded to Pentium II OverDrive processors. The system was upgraded to a total of 9,632 Pentium II Over-Drive processors, each clocked at 333 MHz.
There were a lot of pieces involved in this chip but today’s Pentium Pro consists of two chips and other needed support chips too. Curiously the lead engineer for the 432 was superstar designer Fred Pollack who became the lead architect for the Pentium Pro.
Offenbar hat der PPro einen ladbaren Microcode, für den das Board-BIOS zwei Funktionen im Interrupt 15h zum Auslesen und Laden bereithält (näheres im nächsten Update der Interrupt-Liste). Gedacht ist das für Patches, doch wer weiß, welch ungeahnte Möglichkeiten noch darinstecken. Somit hat man es beim PPro in Zukunft nicht nur mit zwei Masken-Versionen (für CPU und Cache), sondern auch noch mit der Update-Version des Microcode-BIOS zu tun (zum Beispiel beim aktuellen 200-MHz-'P6S' mit der Kennung SY013: CPU-Step A0, Cache-Step B1, BIOS: sA0C05).
The P6 lineage from the Pentium Pro to the Pentium M [...] One of the most distinctive features of the P6 line is its issue port structure. (Intel calls these "dispatch ports," but for the sake of consistency with the rest of my work I'll be using the terms "dispatch" and "issue" differently than Intel.) Core uses a similar structure in its execution core, although there are some major differences between Core's issue port and RS combination and that of the P6.
Integer Leads, FP Lags RISC Chips
The Intel Corporation today introduced its new microprocessor, the Pentium Pro. But although the chip's performance is higher than expected, and its price lower, analysts said its immediate impact was not likely to match that of its predecessor, the Pentium.
Offenbar hat der PPro einen ladbaren Microcode, für den das Board-BIOS zwei Funktionen im Interrupt 15h zum Auslesen und Laden bereithält (näheres im nächsten Update der Interrupt-Liste). Gedacht ist das für Patches, doch wer weiß, welch ungeahnte Möglichkeiten noch darinstecken. Somit hat man es beim PPro in Zukunft nicht nur mit zwei Masken-Versionen (für CPU und Cache), sondern auch noch mit der Update-Version des Microcode-BIOS zu tun (zum Beispiel beim aktuellen 200-MHz-'P6S' mit der Kennung SY013: CPU-Step A0, Cache-Step B1, BIOS: sA0C05).
The P6 lineage from the Pentium Pro to the Pentium M [...] One of the most distinctive features of the P6 line is its issue port structure. (Intel calls these "dispatch ports," but for the sake of consistency with the rest of my work I'll be using the terms "dispatch" and "issue" differently than Intel.) Core uses a similar structure in its execution core, although there are some major differences between Core's issue port and RS combination and that of the P6.
