Asanovic, Krste et al. (ngày 18 tháng 12 năm 2006). "The Landscape of Parallel Computing Research: A View from Berkeley" (PDF). University of California, Berkeley. Technical Report No. UCB/EECS-2006-183. "Old [conventional wisdom]: Increasing clock frequency is the primary method of improving processor performance. New [conventional wisdom]: Increasing parallelism is the primary method of improving processor performance... Even representatives from Intel, a company generally associated with the 'higher clock-speed is better' position, warned that traditional approaches to maximizing performance through maximizing clock speed have been pushed to their limit."
Kahng, Andrew B. (ngày 21 tháng 6 năm 2004) "Scoping the Problem of DFM in the Semiconductor IndustryLưu trữ 2012-03-03 tại Wayback Machine." University of California, San Diego. "Future design for manufacturing (DFM) technology must reduce design [non-recoverable expenditure] cost and directly address manufacturing [non-recoverable expenditures] – the cost of a mask set and probe card – which is well over $1 million at the 90 nm technology node and creates a significant damper on semiconductor-based innovation."
S.V. Adve et al. (November 2008). "Parallel Computing Research at Illinois: The UPCRC Agenda"Lưu trữ 2008-12-09 tại Wayback Machine (PDF). Parallel@Illinois, University of Illinois at Urbana-Champaign. "The main techniques for these performance benefits – increased clock frequency and smarter but increasingly complex architectures – are now hitting the so-called power wall. The computer industry has accepted that future performance increases must largely come from increasing the number of processors (or cores) on a die, rather than making a single core go faster."
Wilson, Gregory V (1994). “The History of the Development of Parallel Computing”. Virginia Tech/Norfolk State University, Interactive Learning with a Digital Library in Computer Science. Truy cập ngày 8 tháng 1 năm 2008.
web.archive.org
S.V. Adve et al. (November 2008). "Parallel Computing Research at Illinois: The UPCRC Agenda"Lưu trữ 2008-12-09 tại Wayback Machine (PDF). Parallel@Illinois, University of Illinois at Urbana-Champaign. "The main techniques for these performance benefits – increased clock frequency and smarter but increasingly complex architectures – are now hitting the so-called power wall. The computer industry has accepted that future performance increases must largely come from increasing the number of processors (or cores) on a die, rather than making a single core go faster."
Kahng, Andrew B. (ngày 21 tháng 6 năm 2004) "Scoping the Problem of DFM in the Semiconductor IndustryLưu trữ 2012-03-03 tại Wayback Machine." University of California, San Diego. "Future design for manufacturing (DFM) technology must reduce design [non-recoverable expenditure] cost and directly address manufacturing [non-recoverable expenditures] – the cost of a mask set and probe card – which is well over $1 million at the 90 nm technology node and creates a significant damper on semiconductor-based innovation."
